In for some instructions of Vertex Shader

In this paper we have done the design for some instructions of Vertex Shader and the Pixel Shader separately. In future we make them unified so that we can achieve parallelism hence, can reduce the total area. And then can achieve better performance and efficiency.
This paper presents the design of programmable shader core computing unit using Verilog HDL. As the Vertex and Pixel Shader blocks are programmable. So we have the authority to change or modify the program. Hence, we can achieve a better efficiency by making the Vertex shader and Pixel Shader fixed functional blocks into programmable ones’. Some of instructions take single cycle for execution like addition, maximum, minimum, power, exponential etc. And some of them take two cycles for execution like multiply-add (mad), matrix multiplication etc. The instruction execution is done as SIMD. It consists of totally 32- bit 4 way computing unit architecture. Hence, we can achieve parallelism. Here all the instructions of Vertex shader and Pixel shader are designed and the results are simulated using Cadence simulator. This paper includes many instructions. Some instructions are from Vertex Shader and some them are from Pixel Shader. Shaders give the output results and result will be stored in the dedicated registers.


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